1. Field
The present invention relates to electronic circuits and, more particularly, to electronic circuits for converting a digital signal to a clock phase.
2. Background
The use of high-speed serial communication links in electronic systems continues to grow. High-speed serial communication links can operate according to various standards such as USB, HDMI, SATA, and PCIe. A serializer/deserializer (SERDES) transmits and receives data from a serial communication link.
FIG. 1 is a functional block diagram of a deserializer (also referred to as a clock and data recovery circuit or CDR). The deserializer is a “half-rate” design in which the frequency of the clock signals is one-half the data rate.
A sampler module 111 samples received data (RX) based on sampling clock signals Φ0, Φ90, Φ180, Φ270 from a digital-to-phase converter 121. The sampling clock signals may be referred to as 0-, 90-, 180-, 270-degree clock signals according to their relative timing. The digital-to-phase converter 121 (also referred to as a phase interpolator) produces the sampling clock signals by interpolating from in-phase and quadrature clock signals (I/Q CLOCKS) (e.g., received from a PLL). The in-phase and quadrature clock signals are differential (complementary) signals with the quadrature clock signal shifted 90 degrees from the in-phase clock signal. The digital-to-phase converter 121 produces the sampling clock signals with a phase (relative to the in-phase and quadrature clock signals) based on a phase control (PHASE) from a loop filter module 131.
The loop filter module 131 uses the sampled received data from the sampler module 111 to produces the phase control. The loop filter module 131 generally operates to place the 0 and 180 degree sampling clock signals on the centers of the received data and the 90 and 270 degree sampling clock signals on the edges of the received data. The 0-degree and 180-degree clock signals can then be used to sample the received data signal to produce the recovered data, and the 90-degree and 270-degree clock signals can be used to sample the received data signal with the samples used for timing recovery.
A data deserializer module 141 converts data samples from the sampler module 111 from serial to parallel format. For example, the data deserializer module 241 may combine five sets of samples of the received data signal that were sampled using the 0 degree and 180 degree clock signals to produce a 10-bit parallel output (DATA).
Prior digital-to-phase converters use current-mode logic (CML) but other circuits (including samplers and PLLs) may use complementary-metal oxide semiconductor (CMOS) logic. Thus, CML-to-CMOS converters are used on the inputs and CMOS-to-CML converters are used on the outputs. The converters can be complex to design and expensive to manufacture. Further, CML circuits do not scale well with shrinking fabrication technology. Additionally, prior digital-to-phase converters can be inaccurate and have a nonlinear relationship between the phase control and the phase of the sampling clock signals.